High-performance computer (HPC) systems typically use multi-processors, including processors with multiple cores and multiple physical processors, also referred to as multiple sockets, all of which interoperate to increase computing power. HPC systems often use dynamic random access memory (DRAM) data caches to reduce the number of off-socket requests for data by keeping data local. Because the multi-processors typically share memory as well as maintain the caches for faster memory access, global cache directories are maintained to insure cache coherence. Cache coherence refers to the uniformity of shared data that is stored in multiple local caches.
Maintaining global cache directories is often accomplished by tracking the data in the DRAM caches and replacing or removing outdated cache entries from the global cache directory as needed using a process referred to as “invalidation.” However, tracking data to maintain coherence incurs a large amount of overhead in the global directory. As the number of processors grows the size of the global cache directory grows, thereby increasing overhead and impacting performance.
Other features of the described embodiments will be apparent from the accompanying drawings and from the detailed description that follows.